1. Field of the Invention
The present invention relates to semiconductor memories. More particularly, the present invention relates to testing semiconductor memories having serial interfaces particularly, but not limited to, EPROM, EEPROM, and flash memories.
2. The Prior Art
Because of their superior characteristics with respect other storage devices, semiconductor memories have become ubiquitous in many modern electronic appliances and systems. Moreover, the push for high integration has led to a dramatic increase of storage capability in a reduced silicon area, hence decreasing memory costs.
Among these devices, flash memories are electrical programmable and erasable non-volatile memories, and are thus particularly suitable for portable data storage applications such as mobile phones, digital still cameras, mp3 players and others.
Semiconductor memory testing is one of the most important phases of manufacturing and is a key factor for device profitability. Various tests are needed to verify a memory device. Examples include testing of embedded reference voltage or current generators, testing of internal control logic, testing of the matrix cells operations such as read, program or erase, and others.
To minimize fabrication costs and to decrease the product time-to-market, different tests are performed at different times and different levels while manufacturing a semiconductor memory. A major distinction can be made between off-line tests, i.e. tests that are performed at an early stage of the device production to solve problems with major impacts on yield, and in-line tests or production tests that are performed when the device is in line for high-volume production. The latter tests impact directly on device cost because they are proportional to the number of devices fabricated, therefore the test time per unit must be minimized.
The use of external voltages for memory testing is common in parallel interface devices. For example, in flash memories the external voltage level can be generated by a variable voltage generator and can be used to measure the cell-voltage threshold distribution, to program or erase a memory cell or group of cells, and for other tests.
Parallel interface memories have one or more dedicated pins that can be used during testing to supply the external voltage level to the memory circuits. FIG. 1 is a block diagram that shows an example of a parallel interface flash memory having data pins (I/O), address pins (ADD), a clock pin (CLK), and one dedicated pin (EXT) for supplying external voltages.
The external voltage pin is not provided in serial interface memories. Excluding power supply connections, such memories have only two pins, a clock pin (CLK) and the data/address pin (DA). A typical memory with such a serial interface is represented as a block diagram in FIG. 2.
To decrease the testing time per unit, it is known that many parallel interface memories can be tested simultaneously by coupling them to a memory tester as shown in the block diagram of FIG. 3. To accomplish simultaneous test on parallel devices a reduction on the number of pins driven by the test equipment is often necessary. A minimum of two pins might be provided as in serial interface devices. In such a case, the EXT pin cannot be used as shown in FIG. 3. Simultaneous testing of serial interface memory devices is also performed as shown in FIG. 4.
FIG. 5 is a block diagram of a prior-art flash memory device having a serial interface. The DA pin sends and collects data to and from DA bidirectional buffer. The direction of the DA buffer (input or output) is controlled by a serial interface logic block by means of signal DA_OUT, i.e. DA_OUT=0 enables the DA buffer as an input buffer to receive data input at the DA pin, and DA_OUT=1 enables the DA buffer as an output buffer to place output data on the DA pin. The CLK pin is an input pin and the CLK buffer is a single-direction input buffer. Serial interface logic is connected to the internal logic or microcontroller via handshake protocol or handshake logic as is known in the art. The internal logic or internal microcontroller drives a read-voltage generator and a modify-voltage generator to supply, respectively, read voltage levels and program or erase voltage levels to the memory matrix array via memory drivers depending on the operation to be performed. Read amplifiers and program buffers are connected between the serial interface logic and the memory drivers.